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Introduction to VLSI

The stundents learn how to effienctly a digital system with SystrmVerilog. They will learn how to map a descprition onf paper, e.g., FSM and datapath, efficiently on an FPGA. The students work in groups of two as this will train their teamwork abilities. A continous examniation is applied, where the student have to deliver a small assignment (project) every fortnight over a 9 weeks time period. Examnination is based on these projects.

SemesterWinter
ECTS7,5
StructureLectures, Excercises, Projects
LanguageEnglish
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